1. Field
The present inventive concepts relate to a semiconductor device and a phase-locked loop (PLL) including the same.
2. Description of the Related Art
Phase-locked loops (PLLs) are commonly used in many electronics circuits and are particularly important in communication circuits. For example, digital systems use clock signals to trigger synchronous circuits, e.g., flip-flops. Transmitter and receiver systems use local oscillator (LO) signals for frequency upconversion and downconversion, respectively. Wireless devices (e.g., cellular phones) in wireless communication systems typically use clock signals for digital circuitry and LO signals for transmitter and receiver circuitry. Clock and LO signals are often generated with voltage-controlled oscillators (VCOs) operating within PLLs.
A PLL typically includes a phase frequency detector (PFD), a charge pump, a loop filter, and a VCO. The PFD, the charge pump, and the loop filter collectively detect phase error between a reference signal and a clock signal derived from the VCO and generate a control signal Vctrl for the VCO. The control signal adjusts the frequency of the VCO such that the clock signal is locked to the reference signal.
A current mismatch that occurs in the charge pump during the operation of the PLL increases the jitter of the PLL. To prevent this problem, only a part in which the difference between an up signal and a down signal input to the charge pump is small may be used. However, this can limit the operating range of the charge pump.